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Synchronous Step-Down MOSFET Drivers
ZL1505
The ZL1505 is an integrated high-speed, high-current N-channel MOSFET driver for synchronous step-down DC-DC conversion applications. When used with Zilker Labs Digital-DCTM PWM controllers, the ZL1505 enables dynamically adaptive dead-time control that optimizes efficiency under all operating conditions. A dual input PWM configuration enables this efficiency optimization while minimizing complexity within the driver. Operating from a 4.5V to 7.5V input, the ZL1505 combines a 5A, 0.5W low-side driver and a 3A, 0.8W high-side driver to support high step-down buck applications. A unique adjustable gate drive current scheme allows the user to adjust the drive current on both drivers to optimize performance for a wide rage of input/output voltages, load currents, power MOSFETs and switching frequencies up to 1.4MHz. An integrated 30V bootstrap Schottky diode is used to charge the external bootstrap capacitor. An internal watchdog circuit prevents excessive shoot-through currents and protects the external MOSFET switches. The ZL1505 is specified over a wide -40C to +125C junction temperature range and is available in an exposed pad DFN-10 package.
ZL1505
Features
* High-speed, high-current drivers for synchronous N-channel MOSFETs * Adaptive dead-time control optimizes efficiency when used with Digital-DC controllers * Integrated 30V bootstrap Schottky diode * Capable of driving 40A per phase * Supports switching frequency up to 1.4MHz - >4A source, >5A sink low-side driver - >3A source/sink high-side driver - <10ns rise/fall times, low propagation delay * Adjustable gate drive strength optimizes efficiency for different VIN, VOUT, IOUT, FSW and MOSFET combinations * Internal non-overlap watchdog prevents shoot-through currents
Applications*(see page 12)
* High efficiency, high-current DC/DC buck converters with digital control and PMBusTM * Multi-phase digital DC/DC converters with phase adding/dropping * Power train modules * Synchronous rectification for secondary side isolated power converters
Related Literature*(see page 12)
* FN6846 ZL2004 Data Sheet
HSEL VDD PWMH Level shift PWML
Shootthrough Protection
BST GH SW
VDD
GL
ZL1505
GND LSEL
FIGURE 1. ZL1505 BLOCK DIAGRAM
December 4, 2009 FN6845.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ZL1505
Typical Application Circuit
The following application circuit represents the typical implementation of the ZL1505 (Notes 1, 2).
VIN 4.5-14V
VBIAS 4.5-7.5V
VIN VDD VMON
LSEL HSEL BST VDD
VIN
Power Train Module
GH SW PWMH
PWMH
ZL2004
PWML XTEMP SGND VSE N+ VSE NISENA ISENB
PWMH PWML TEMP+
VOUT
ZL1505
PWML GND
GL
GND
TEMP-
GND
CS+
CS-
FIGURE 2. POWER TRAIN MODULE USING ZL2004 PWM CONTROLLER NOTES: 1. For VDD of 4.5V to 7.5V, the maximum VIN of the ZL1505 is 22.5V to 25.5V. ZL1505 input supply voltage range (VIN) is specified in Figure 2. 2. VIN for this application circuit is limited by the ZL2004 VIN of 4.5V to 14V.
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FN6845.1 December 4, 2009
ZL1505
Pin Configuration
ZL1505 (10 LD DFN) TOP VIEW
HSEL 1 GH 2 SW 3 PWMH 4 PWML 5 *CONNECT TO GND *EPAD 10 BST 9 VDD 8 GL 7 GND 6 LSEL
Pin Descriptions
PIN NUMBER 1 PIN NAME HSEL TYPE (Note 3) I DESCRIPTION High-side gate drive current selector. Connect to BST for maximum gate drive current; Connect to SW for 50% of maximum gate drive current.
2 3 4 5 6
GH SW PWMH PWML LSEL
O I/O I I I
Output of high-side gate driver. Connect to the gate of high-side FET. Phase node. Return path for high-side driver. Connect to source of high-side FET and drain of low-side FET. High-side PWM control input. Low-side PWM control input. Low-side gate drive current selector. Connect to VDD for maximum gate drive current; Connect to GND for 50% of maximum gate drive current. Ground. All signals return to this pin. Output of low-side gate driver. Connect to the gate of low-side FET. Gate drive bias supply. Connect a high quality bypass capacitor from this pin to GND. Bootstrap supply. Connect external capacitor to SW node. Ground.
7 8 9 10 ePad NOTE:
GND GL VDD BST GND
PWR O PWR PWR PWR
3. I = Input, O = Output, PWR = Power OR Ground.
Ordering Information
PART NUMBER (Notes 4, 5, 6) ZL1505ALNNT ZL1505ALNNT1 NOTES: 4. Please refer to TB347 for details on reel specifications. 5. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 6. For Moisture Sensitivity Level (MSL), please see device information page for ZL1505. For more information on MSL please see techbrief TB363. PART MARKING 1505 1505 TEMP RANGE (C) -40 to +125 -40 to +125 PACKAGE Tape and Reel (Pb-free) 10 Ld 3x3 DFN 10 Ld 3x3 DFN PKG. DWG. # L10.3x3D L10.3x3D
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FN6845.1 December 4, 2009
ZL1505
Absolute Maximum Ratings
Voltage Measured with Respect to GND DC Supply Voltage for VDD Pin . . . . . . . . . . . . . -0.3V to 8V High-Side Supply Voltage for BST Pin . . . . . . . . -0.3V to 30V High-Side Drive Voltage for GH Pin . . . . . . . . . . . . . . . (VSW - 0.3V) to (VBST + 0.3V) Low-Side Drive Voltage for GL Pin . . . . . . . . . . . . . . . . (GND - 0.3V) to (VDD + 0.3V) Boost to Switch Differential (VBST - VSW) for BST, SW Pins . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 8V Switch Voltage for SW Pin Continuous . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to 30V <100ns . . . . . . . . . . . . . . . . . . . . . . . (GND - 5V) to 30V Logic I/O Voltage for PWMH, PWML, LSEL Pins . . . -0.3V to 8V HSEL Pin . . . . . . . . . . . . . (VSW - 0.3V) to (VBST + 0.3V) ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . 2kV GL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V Latch Up . . . . . . . . . . . . . . . . . . . . . . . . Tested to JESD78
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Ld DFN (Notes 7, 8) . . . . . . . . . 50 7 Junction Temperature Range . . . . . . . . . . -55C to +150C Storage Temperature Range . . . . . . . . . . . -55C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Gate Drive Bias Supply Voltage Range VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 7.5V Input Supply Voltage Range, VIN . . . . . . . . 3V to 30V - VDD Operating Junction Temperature Range, TJ . . -40C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 8. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = 6.5V, TJ = -40C to +125C unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply over the operating temperature range, -40C to +125C. CONDITIONS MIN MAX (Note 9) TYP (Note 9) UNIT
PARAMETER BIAS CURRENT CHARACTERISTICS IDD supply current PWM INPUT CHARACTERISTICS PWM input bias current VPWM = 5 V VPWM = 0 V PWM input logic low, VIL PWMH or PWML Not switching
-
110
180
A
- - VDD = 6.5V VDD = 5.0 V 1.7 1.5 2.8 2.2 -
5 - 2 1.7 3.1 2.5 1.1 0.8 8.5
- 1 2.2 1.9 3.4 2.7 12
A A V V V V V V ns
PWM input logic high, VIH
PWMH or PWML
VDD = 6.5V VDD = 5.0V
Hysteresis
PWMH or PWML
VDD = 6.5V VDD = 5.0V
Minimum PWMH On-time to Produce GH Pulse, tPWMH,ON (Note 10) Minimum GH On-time pulse, tGH,ON (Note 11) Minimum PWMH Off-time to Produce Valid GH Pulse, tPWMH,OFF
CGH = 0
CGH = 0 CGH = 3 nF, VHSEL = VBST CGH = 0
- -
10 14 13
14 20 17
ns ns ns
BOOTSTRAP DIODE CHARACTERISTICS Forward Voltage (VF) Forward bias current 100 mA - 0.8 - V
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FN6845.1 December 4, 2009
ZL1505
Electrical Specifications
VDD = 6.5V, TJ = -40C to +125C unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued) CONDITIONS MIN MAX (Note 9) TYP (Note 9) UNIT
PARAMETER THERMAL PROTECTION Thermal trip point Thermal reset point UPPER GATE DRIVER CHARACTERISTICS Driver Voltage (VBST - VSW) High-side Driver Peak Gate Drive Current (Pull-up)
- -
150 134
- -
C C
- (VGH - VSW) = 2.5V HSEL connected to BST HSEL connected to SW 2.0 1.0 2.0 1.0 - -
6 3.2 1.7 3.2 1.6 0.7 0.9 0.8 1.1
- - - 0.9 1.2 1.1 1.5
V A A A A
High-side Driver Peak Gate Drive Current (Pull-down)
(VGH - VSW) = 2.5V
HSEL connected to BST HSEL connected to SW
High-side Driver Pull-up Resistance
(VBST - VGH) = 50mV
HSEL connected to BST HSEL connected to SW
High-side Driver Pull-down Resistance
(VGH - VSW) = 50mV
HSEL connected to BST HSEL connected to SW
LOWER GATE DRIVER CHARACTERISTICS Driver voltage (VDD) Low-side Driver Peak Gate Drive Current (Pull-up) (VGL - VGNG) = 2.5V LSEL connected to VDD LSEL connected to GND Low-side Driver Peak Gate Drive Current (Pull-down) (VGL - VGND) = 2.5V LSEL connected to VDD LSEL connected to GND Low-side Driver Pull-up Resistance (VDD - VGL) = 50mV LSEL connected to VDD LSEL connected to GND Low-side Driver Pull-down Resistance (VGL - GND) = 50mV LSEL connected to VDD LSEL connected to GND SWITCHING CHARACTERISTICS GH rise time, tRH CGH = 3nF HSEL connected to BST HSEL connected to SW - 5.3 10.5 8.5 16.5 ns ns 3.0 1.5 3.5 1.8 - - 6.5 4.5 2.4 5.4 2.8 0.7 1.0 0.5 0.7 - - 0.9 1.3 0.7 1.0 V A A A A
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FN6845.1 December 4, 2009
ZL1505
Electrical Specifications
VDD = 6.5V, TJ = -40C to +125C unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued) CONDITIONS CGH = 3nF HSEL connected to BST HSEL connected to SW GL rise time, tRL CGL = 3nF LSEL connected to VDD LSEL connected to GND GL fall time, tFL CGL = 3nF LSEL connected to VDD LSEL connected to GND GH turn-on propagation delay, tDHR HSEL connected to BST HSEL connected to SW GH turn-off propagation delay, tDHF HSEL connected to BST HSEL connected to SW GL turn-on propagation delay, tDLR LSEL connected to VDD LSEL connected to GND GL turn-off propagation delay, tDLF LSEL connected to VDD LSEL connected to GND NOTES: 9. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. The minimum PWMH on-time pulse (tPWMH,ON) is specified from VPWM = 2.5V on the rise edge to VPWM = 2.5V on the falling edge. 11. The minimum GH on-time pulse (tGH,ON) is specified at VGH = 2.5V. MIN MAX (Note 9) TYP (Note 9) UNIT - - - - - 4.8 9.5 4.0 7.8 3.0 5.5 30.0 31.5 37.5 39.0 26.5 28.0 30.0 31.5 7.5 15 6.0 12 4.5 8.5 - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER GH fall time, tFH
PWM
2.5V
2.5V
tPWMH,ON tDLF tDLR
90% 2.5V 10% 90% 2.5V
GH
tRH
tGH,ON tFH
10%
FIGURE 3. TIMING DIAGRAM
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ZL1505
Typical Performance Curves
130 120 110 IVDD (uA) 100 90
130 T (C) 155 150 145 140 135
80 70 4.5 5 5.5 6 VDD (V) 6.5 7
-25 C 25 C 85 C 7.5
125 120 4.5 5 5.5 6 VDD (V) 6.5
Trising Tfalling 7 7.5
FIGURE 4. IVDD vs VDD WITH TEMPERATURE (NO SWITCHING)
FIGURE 5. THERMAL PROTECTION THRESHOLDS
22 20 18 On-time (ns)
CGH=0 CGH=3nF, HSEL=BST CGH=3nF, HSEL=SW
16 15 14 On-time (ns) 13 12 11 10 9 8
-25 C 25 C 85 C
16 14 12 10 8 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
4.5
5
5.5
6 VDD (V)
6.5
7
7.5
FIGURE 6. MINIMUM GH ON-TIME, tGH,ON (Note 12, TA = +25C) NOTES:
FIGURE 7. tGH,ON WITH TEMPERATURE (Note 13, CGH = 0)
12. Performance curves with temperature are measured at ambient temperatures (TA) of +85C, +25C and -25C. 13. tGH,ON timing is shown in Figure 3.
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FN6845.1 December 4, 2009
ZL1505
Typical Performance Curves (Continued)
16 14
30
-25 C 25 C 85 C
26
12 On-time (ns)
Off-time (ns)
-25 C 25 C 85 C 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
10 8 6
22
18
14
4 2
10 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
FIGURE 8. MINIMUM PWMH ON-TIME, tPWMH,ON (CGH = 0)
6.6 5.6 4.6 IGL (A) 3.6 2.6
FIGURE 9. MINIMUM PWMH OFF-TIME, tPWMH,OFF (CGH = 0)
6.6
5.6
IGL (A)
4.6
3.6 -25 C
1.6 0.6 4.5 5 5.5 6 VDD (V) 6.5
2.6
LSEL=VDD LSEL=GND 7 7.5
25 C 85 C
1.6 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
FIGURE 10. LOW-SIDE DRIVER PULL-UP CURRENT (VGL = 2.5V, TA = +25C)
FIGURE 11. LS PULL-UP CURRENT WITH TEMPERATURE (VGL = 2.5V, LSEL = VDD)
8 7
8
7
6 IGL (A) 5 4 3
IGL (A)
6
5 -25 C 4
2 1 4.5 5 5.5 6 VDD (V) 6.5
LSEL=VDD LSEL=GND 7 7.5
25 C 85 C
3 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
FIGURE 12. LOW-SIDE DRIVER PULL-DOWN CURRENT (VGL = 2.5V, TA = +25C)
FIGURE 13. LS PULL-DOWN CURRENT WITH TEMPERATURE (VGL = 2.5V, LSEL = VDD)
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FN6845.1 December 4, 2009
ZL1505
Typical Performance Curves (Continued)
12 11 10 9 trise (ns) LSEL=VDD LSEL=GND
6.5 6 5.5 trise (ns) 5 4.5 4
-25 C 25 C 85 C
8 7 6 5 4 3 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
3.5 3 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
FIGURE 14. LOW-SIDE DRIVER RISE TIME, tRL (CGL = 3nF, TA = +25C)
FIGURE 15. tRL WITH TEMPERATURE (CGL = 3nF, LSEL = VDD)
7 LSEL=VDD LSEL=GND 6
4.5 -25 C 4 25 C 85 C
tfall (ns)
tfall (ns)
5
3.5
4
3
3
2.5
2 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
2 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
FIGURE 16. LOW-SIDE DRIVER FALL TIME, tFL (CGL = 3nF, TA = +25C)
5
FIGURE 17. tFL WITH TEMPERATURE (CGL = 3nF, LSEL = VDD)
5 4.5
4
4
IGH (A)
IGH (A)
3
3.5 3 2.5 2
2
1 HSEL=BST 0 4.5 5 5.5 6 VDD (V) 6.5 HSEL=SW
-25 C 1.5 1 25 C 85 C 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
7
7.5
FIGURE 18. HIGH-SIDE DRIVER PULL-UP CURRENT (VGH - VSW = 2.5V, TA = +25C)
FIGURE 19. HS PULL-UP CURRENT WITH TEMPERATURE (VGH - VSW = 2.5V, HSEL = BST)
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FN6845.1 December 4, 2009
ZL1505
Typical Performance Curves (Continued)
5
5 4.5 4
4
IGH (A)
IGH (A)
3 2
3.5 3 2.5
1
HSEL=BST
-25 C
2 1.5 4.5 5 5.5 6 VDD (V) 6.5 7
0 4.5 5 5.5 6 VDD (V) 6.5
HSEL=SW
25 C 85 C
7
7.5
7.5
FIGURE 20. HIGH-SIDE DRIVER PULL-DOWN CURRENT (VGH - VSW = 2.5V, TA = +25C)
FIGURE 21. HS PULL-DOWN CURRENT WITH TEMPERATURE (VGH - VSW = 2.5V, HSEL = BST)
17.5 15.5 13.5 trise (ns) 11.5 9.5 7.5 5.5 3.5 4.5 5 5.5 6 VDD (V) 6.5
HSEL=BST HSEL=SW
8.5
-25 C 25 C 85 C
7.5
trise (ns) 7 7.5
6.5
5.5
4.5
3.5 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
FIGURE 22. HIGH-SIDE DRIVER RISE TIME, tRH (CGH = 3nF, TA = +25C)
11.5
FIGURE 23. tRH WITH TEMPERATURE (CGH = 3nF, HSEL = BST)
HSEL=BST HSEL=SW
7.5
-25 C 25 C 85 C
9.5 tfall (ns) tfall (ns) 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
6.5
7.5
5.5
5.5
4.5
3.5
3.5 4.5 5 5.5 6 VDD (V) 6.5 7 7.5
FIGURE 24. HIGH-SIDE DRIVER FALL TIME, tFH (CGH = 3nF, TA = +25C)
FIGURE 25. tFH WITH TEMPERATURE (CGH = 3nF, HSEL = BST)
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FN6845.1 December 4, 2009
ZL1505
ZL1505 Overview
Theory of Operation
The ZL1505 is a synchronous N-channel MOSFET driver that is intended for use with Zilker Labs Digital-DC PWM controllers to enable a high-efficiency DC/DC conversion scheme. The patented Digital-DC control scheme utilizes a closed-loop algorithm to optimize the dead-time applied between the gate drive signals for the high-side and low-side MOSFETs. By monitoring the duty cycle of the resulting DC/DC converter circuit, this dynamic routine continuously varies the MOSFET dead times to optimize conversion efficiency in response to varying circuit conditions. The ZL1505's dual PWM input configuration enables this optimization scheme to be applied while minimizing the complexity within the driver device. Please refer to the ZL2004 data sheet for details on the dynamic dead-time optimization routine. The ZL1505 integrates two powerful gate drivers that have been optimized for step-down DC/DC conversion circuit configurations whose output current can exceed 40A per phase. The ZL1505 also integrates a 30V bootstrap Schottky diode to minimize the external components and provide a high drive voltage to the high-side driver device.
condition ceases, allowing normal switching operation to continue.
Start-up Requirements
During power-up, the ZL1505 maintains both GH and GL outputs in the LOW state while the VIN voltage is ramping up. Once the VDD supply is within specification, the GH and GL pins may be operated using the PWMH and PWML logic inputs respectively. In the case where the PWM controller is powered from a supply other than the ZL1505's VDD supply, and the PWM controller is powered up first, the PWM controller gate outputs should be kept in low or in high-impedance state until the VDD supply is within specification. Additionally, if the ZL1505 begins its power-down sequence prior to the PWM controller then the PWM controller gate outputs should be set in low or in high-impedance state before the VDD voltage supply drops below its specified range.
Thermal protection
When the junction temperature exceeds +150C the high-side driver output GH is forced to logic low state. The driver output is allowed to switch logic states again once the junction temperature drops below +134C.
Variable Gate Drive Current
The ZL1505 incorporates an innovative variable drive current scheme that enables the user to optimize the gate drive current levels to the requirements of the external MOSFETs used over a wide range of operating frequencies. Each of the gate drivers incorporates a logic input (HSEL and LSEL) that allows the user to select the gate drive strength to 50% or 100% of the total rated drive current. With the HSEL pin connected to the BST pin, the high-side driver can deliver the full rated gate drive current; with the HSEL pin connected to the SW pin, the output current will be limited to 50% of the full rated output capability. With the LSEL pin connected to VDD, the low-side driver can deliver the full rated gate drive current; with the LSEL pin connected to GND, the output current will be limited to 50% of the full rated output capability. Using HSEL and LSEL, the ZL1505 can be used across a wide range of applications using only a simple PCB layout change. Also, the VDD pin is the gate drive bias supply for the external MOSFETs. VDD can be used to vary the gate drive strength as shown for the low-side driver in Figures 9 thru 12 and for the high-side driver in Figures 17 thru 20.
Overlap Protection Circuit
The ZL1505 includes an internal watchdog circuit that prevents excessive shoot-through current from occurring in the unlikely event that the PWM converter places both switches in the ON position. If the overlap time between the PWMH and PWML pulses exceeds 30ns, the PWMH signal will be forced to the LOW state until the overlap 11
FN6845.1 December 4, 2009
ZL1505
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 12/4/09 REVISION FN6845.1 CHANGE Converted to new Intersil template. Changed in Abs Max Ratings "Low-Side Drive Voltage for GL pin" from "(GND - 0.3) to (VIN + 0.3)" to "(GND - 0.3) to (VDD + 0.3)". Removed Bullet "Adjustable gate drive voltage: 4.5V to 7.5V" and "Exposed pad 3mmx3mm DFN-10 Package" from Features. Intersil Standards applied are: Added Related Information, Updated ordering information with Notes that includes MSL. Updated Abs Max Ratings with notes, added ESD Ratings and Latchup, added Boldface text in Electrical Spec Table. Added POD Assigned file number FN6845 to datasheet as this will be the first release with an Intersil file number. Replaced header and footer with Intersil header and footer. Updated disclaimer information to read "Intersil and it's subsidiaries including Zilker Labs, Inc." No changes to datasheet content
2/14/09
FN6845.0
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ZL1505 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6845.1 December 4, 2009
ZL1505 Dual Flat No-Lead Plastic Package (DFN)
D A B N N-1
L10.3x3D
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.80 0.00 NOMINAL 0.85 0.02 0.20 REF 0 0.20 MIN 3.00 BSC 2.20 2.30 3.00 BSC 1.50 0.35 1.60 0.40 0.15mm MAX 0.18 0.25 0.50 BSC 10 5 0.30 1.70 0.45 2.40 12 11 4 3 5 Rev. 0 3/09 12 MAX 0.90 0.05 NOTES 2
8. 0.20 DIA TYP E
A A1 A3 K
TOP VIEW
2X 2X
0.10 0.10
C 1 C 2
D D2 E
0.10 9.
C A C
E2 L L1
A1
0.05
C
SEATING PLANE
b e N ND
SIDE VIEW
D2 (DATUM A) D2/2 PIN #1 ID R0.20 1 2 NX L (DATUM B) E2/2 E2 9.
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. All dimensions are in millimeters. is in degrees. 3. N is the number of terminals. 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 5. ND refers to the number of terminals on D side. 6. Max package warpage is 0.05m. 7. Maximum allowable burrs is 0.076mm in all directions. 8. Pin #1 ID on top will be laser marked 9. Bilatteral coplaniarity zone applies to the exposed heat sink slug as well as the terminals. 10. This drawing conforms to JEDEC registered outline M0-229. 11. Depending on the method of lead termination at the edge of the package, pullback (L1) may be present.
K SEE DETAIL "A" 5.
N N-1 e (ND-1) X e
NX b
4.
0.10 M C A B 0.05 M C
BOTTOM VIEW
DATUM A OR B
12. Pullback design option is for 0.50mm nominal landlength only.
L1 11.
L1 11. L e e/2 4. TERMINAL TIP L e
DETAIL "A"
13
FN6845.1 December 4, 2009

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